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Sophisticated tool optimizations are often not good enough to meet most design
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constraints if an arbitrary coding style is used. This chapter discusses the rst of three primary physical characteristics of a digital design: speed. This chapter also discusses methods for architectural optimization in an FPGA. There are three primary de nitions of speed depending on the context of the problem: throughput, latency, and timing. In the context of processing data in an FPGA, throughput refers to the amount of data that is processed per clock cycle. A common metric for throughput is bits per second. Latency refers to the time between data input and processed data output. The typical metric for latency will be time or clock cycles. Timing refers to the logic delays between sequential elements. When we say a design does not meet timing, we mean that the delay of the critical path, that is, the largest delay between ip- ops (composed of combinatorial delay, clk-to-out delay, routing delay, setup timing, clock skew, and so on) is greater than the target clock period. The standard metrics for timing are clock period and frequency. During the course of this chapter, we will discuss the following topics in detail:
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High-throughput architectures for maximizing the number of bits per second that can be processed by the design. Low-latency architectures for minimizing the delay from the input of a module to the output. Timing optimizations to reduce the combinatorial delay of the critical path. Adding register layers to divide combinatorial logic structures. Parallel structures for separating sequentially executed operations into parallel operations. Flattening logic structures speci c to priority encoded signals. Register balancing to redistribute combinatorial logic around pipelined registers. Reordering paths to divert operations in a critical path to a noncritical path.
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Advanced FPGA Design. By Steve Kilts Copyright # 2007 John Wiley & Sons, Inc.
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1 Architecting Speed
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HIGH THROUGHPUT
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A high-throughput design is one that is concerned with the steady-state data rate but less concerned about the time any speci c piece of data requires to propagate through the design (latency). The idea with a high-throughput design is the same idea Ford came up with to manufacture automobiles in great quantities: an assembly line. In the world of digital design where data is processed, we refer to this under a more abstract term: pipeline. A pipelined design conceptually works very similar to an assembly line in that the raw material or data input enters the front end, is passed through various stages of manipulation and processing, and then exits as a nished product or data output. The beauty of a pipelined design is that new data can begin processing before the prior data has nished, much like cars are processed on an assembly line. Pipelines are used in nearly all very-high-performance devices, and the variety of speci c architectures is unlimited. Examples include CPU instruction sets, network protocol stacks, encryption engines, and so on. From an algorithmic perspective, an important concept in a pipelined design is that of unrolling the loop. As an example, consider the following piece of code that would most likely be used in a software implementation for nding the third power of X. Note that the term software here refers to code that is targeted at a set of procedural instructions that will be executed on a microprocessor.
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XPower = 1; for (i=0;i < 3; i++) XPower = X * XPower;
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Note that the above code is an iterative algorithm. The same variables and addresses are accessed until the computation is complete. There is no use for parallelism because a microprocessor only executes one instruction at a time (for the purpose of argument, just consider a single core processor). A similar implementation can be created in hardware. Consider the following Verilog implementation of the same algorithm (output scaling not considered):
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module power3( output [7:0] output input [7:0] input reg reg XPower, finished, X, clk, start); // the duration of start is a single clock [7:0] ncount; [7:0] XPower;
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