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time of writing and can be found in many mobile phones. ARM926EJ cache lines are eight words long, so to be aligned, an address must be divisible by 32.
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18.1.6 Pragmatism, not idealism
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Unfortunately, there is only a nite amount of work that any processor can do in one second, and that amount depends on the nature of the work. While the processors available to mobile phone applications now would have been astonishingly powerful as recently as ten years ago, they aren t that powerful compared to workstation processors. Mobile phone manufacturers have to choose processors based on their benchmark scores. That is, they use gures published by manufacturers, measured using programs designed to advertise how fast their processors are. The problem with this is that the performance of a processor is entirely dependent on what it s being asked to process. The application binary environment, compiler and even the instruction set may have been tweaked to improve benchmark performance! That s all very well as long as your application does the same sort of thing as the benchmark, and only the same sort of thing rather than a mixture of different operations. To make a safer estimate, it s important to have a set of representative, mixed operation benchmarks, timing how long it takes to perform actual user operations, using real applications. The user interface can be as important as the application engine itself in these tests. It s not a simple operation to take a set of benchmark results, perform an examination of a very different problem, and say with certainty that problem x can be solved with processor y in time t . It is, therefore, very important to de ne the scope of your application with this in mind. The manufacturer s benchmarks, such as Dhrystone, running on the bare metal of the machine, may demonstrate performance far in excess of that actually available in a real-time, multithreaded, interruptrich environment. Treat these benchmarks as you do all other forms of advertising!
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18.1.7 Memory throughput
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ARM systems have fairly fast memory systems. They consist of a large DRAM, accessed by the processor through a cache, prefetch buffer and a write buffer. The cache usually consists of around 16 KB of very fast memory, which is usually run at the same speed as the processor core itself. This is necessary in the ARM architecture because almost every cycle will issue an instruction. All ARMv5 and later processors have a write buffer, which is a simple FIFO queue that accepts data to be written to memory. It serves to decouple the processor pipeline from the core s data port so that if the
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cache misses on the data to be written, the processor pipeline does not stall. The size of the FIFO is usually eight words, and the words are usually not required to be ordered in any way. ARM systems today use a wide variety of different interconnects and memory types, but most current systems use synchronous DRAM, similar to SDRAM or DDR RAM, attached to essentially transparent interconnects. These clock at around half the processor core speed, though with the trend towards increased core speeds this is likely to change in the near future. Power consumption and processor package pin count constrain mobile memory systems more than component cost, which means that most mobile platforms use 16-bit wide memory interfaces. This essentially limits the maximum sustained bandwidth of their memory interfaces to one word every four core cycles. This variable remains remarkably consistent across new and old processors. However, in practice this limit can never be achieved. SDRAM is line-oriented, that is, it is designed in such a way that a row address is applied, taking between two and seven cycles depending on the type of RAM, then a column address is applied, returning data usually between two and three cycles later. Subsequent words from the same row can then be fetched in subsequent cycles without delay. This burst mode is very useful in cached architectures like ARM, where whole lines of eight words are generally fetched at any time, and can make memory access several times faster. The exact management of RAM parameters is beyond the scope of this book, but is critical to the performance of the system as a whole. It is very important to ensure that systems have their RAM con gured correctly.
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