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17.4.5 A GSM stack on EKA2
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As an illustration of a real time application running on EKA2, I will consider the implementation of a GSM protocol stack. Obviously, only an outline will be given and not all scenarios will be considered a real stack requires many man-years of development! I will assume that all processing is done on the main ARM processor and there is no DSP while, in principle, this could be achieved on high end ARM devices such as ARM1136, in practice no-one would actually do so,
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REAL TIME APPLICATION GSM
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because it would be inef cient in terms of power consumption, cost and the number of cycles available for application processing. I will assume the following hardware con guration: Timing controller has free running counter at four times the GSM bit rate which wraps to zero at 5000 quarter bits, that is, one GSM frame period There are several match registers that can trigger an event. This event can be an interrupt to the processor, switching on or off some piece of hardware such as the frequency synthesizer, the receive chain or the transmit chain, the start of a receive or the start of a transmission Once a receive starts, the processor is interrupted whenever 16 sample pairs are available and these must be read before the next interrupt occurs Before a transmission starts the data to be transmitted must be loaded into a TX buffer and the power ramp up and ramp down masks must be loaded into a power control buffer Frequency synthesizer needs 500 s to lock before beginning RX or TX Equalizing a received burst, channel encoding or decoding and speech encoding or decoding takes 250 s maximum Scanning for a FCCH burst takes 10 s maximum per 16 sample pairs. A processor interrupt is triggered once every frame in the same place so that a frame count can be maintained.
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17.4.5.1 Frequency burst receive
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The main activities related to FCCH burst reception are shown in Figure 17.6.
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Figure 17.6 Frequency burst search
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In Figure 17.6, the HW line shows what the hardware is doing, the FI line indicates the time of the once-per-frame interrupt and the L1 Task line shows which software tasks are in progress. The tasks involved are: (i) Programming the hardware with the frequency to receive and the time at which to start the receive. This is shown as task P. This task is triggered by the main layer 1 state machine when a frequency burst search is required Reading blocks of 16 sample pairs from HW buffer to main memory buffer. This task is not shown since it is too frequent. It is triggered by the baseband receive ADC interrupt Processing the received samples to search for a frequency burst. This is shown as task F, although it occurs more frequently than is shown. It is triggered by task (ii) On either nding a frequency burst or timing out, shut down the hardware and start the next operation if any. This is shown as task Q. It may be necessary to search for up to 11.25 frame times the worst case occurs when you start the receive just after the beginning of the FCCH burst and the next burst starts in 11 frames. This task is triggered by the per-frame interrupt following either the detection of a frequency burst or a timeout.
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(ii)
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Task (ii) has the shortest deadline (16 bit periods or 59 s), so I will implement this as an ISR. In fact with a hard deadline as short as this, it would be best to use the ARM processor s FIQ interrupt. The other tasks must run in a thread context. It would be inef cient to schedule a thread at this frequency it would use around 10% of the processor time context switching. It is also unnecessary. Instead, task (iii) will be triggered every 10 receive interrupts. The deadline for task (iii) depends on how much buffering is used. If there is enough buffering for 480 sample pairs (around 2 K) the deadline would be 320*3.69 s = 1180 s, since the task is triggered when there are 160 sample pairs available and must complete before the buffer lls. Tasks (i) and (iv) are triggered by the per-frame interrupt and need to complete quickly enough to set up hardware for the following frame. A convenient time for the per-frame interrupt is two timeslots into the frame, since it then does not clash with either the receive or transmit windows and allows six timeslots for any setup to complete before the next frame. This is 3.460 ms. However, 500 s is required for the synthesizer to lock before the next receive and so the deadline for tasks P and Q is 2.9 ms. So task P and Q should have lower priority than task F. In fact in this case the same thread could be used for all three tasks since these tasks never execute simultaneously anyway.
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