Figure 24 Interprocessor communication in LogP in VS .NET

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Figure 24 Interprocessor communication in LogP
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Furthermore, the structure of the processor network is not described by LogP, but its capacity is limited to L/g simultaneous message transfers between all processors An implicit parameter is the message size M, which consists of one or a small number of words Based on this parameter, an interprocessor message transfer in the LogP model proceeds as illustrated in Figure 24 In contrast to PRAM, LogP is an asynchronous model
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22 COMMUNICATION NETWORKS Fast communication is crucial for an ef cient parallel system A determining aspect of the communication behavior is the network and its topology In the previous section, some kind of interconnection network for communication among the units of the parallel system was supposed This section reviews the principal network types, of which each offers a different trade-off between cost and performance Initially, interconnection networks can be classi ed into static and dynamic networks Static networks have xed connections between the units of the system with point-to-point communication links In a dynamic network, the connections between units of the parallel system are established dynamically through switches when requested Based on this difference, static, and dynamic networks are sometimes referred to as direct and indirect networks, respectively (Grama et al [82], Quinn [156]) 221 Static Networks The essential characteristic of a static network is its topology, as the interconnections between the units of the parallel system are xed Most static networks are processor networks used in distributed memory systems, where every processor has its own local memory Processor network topologies are usually represented as undirected graphs2 : a vertex represents a processor, together with its local memory and a switch, and an undirected edge represents a communication link between two processors (Cosnard and Trystram [45], Culler and Singh [48], Grama et al [82]) Figure 25(b) depicts an example for a network graph consisting of four processors Figure 25(a) illustrates the implicit association of memory and a switch with each processor Once a topology is modeled as an undirected graph, terminology from graph theory can be utilized for its characterization The degree of a vertex is de ned as the number of its incident edges, denoted by The eccentricity of a vertex is the largest distance, in terms of the number of edges, from that vertex to any other vertex Furthermore, the diameter of an undirected graph, denoted by D, is de ned as the maximum eccentricity of all vertices of the graph Another notable indicator for a network is its bisection width It is de ned as the minimum number of edges that have to be removed to
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2 Basic graph concepts are introduced in Section 31 and the undirected graph model of topologies will be de ned more formally in Section 71 For the current purpose, this informal de nition suf ces
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Figure 25 An undirected graph representing a processor network (b); (a) an illustration that the switch and the memory associated with each processor are implicit in the common representation of processor networks
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partition the network into two equal halves In other words, it is the number of edges that cross a cut of a network into two equal halves To achieve a network with a small maximum communication time, the goal is to have a small diameter D At the same time, the mean degree of the network should be small, since it determines the hardware costs Last but not least, the network should have a large bisection width, because it lowers the contention for the communication links However, the bisection width is also a measure for the network costs, as it provides a lower bound on the area or volume of its packaging (Grama et al [82]) Fully Connected Networks A network in which every processor has a direct link to any other processor, as depicted in Figure 26, is called fully connected It has
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