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multiples of these nodes are interconnected on a higher level Examples of systems with such a hierarchical memory architecture are the Sequent NUMA-Q, the SGI Origin 2000/3000 series, and the IBM Blue Gene/L (van der Steen and Dongarra [193]), which is the world s fastest computer at the time this is written [186] Motivations The following paragraphs brie y look at the motivations for the different architectures Centralized shared-memory architectures are an intuitive extension of a single processor architecture; however, the contention for the communication resources to the central memory signi cantly limits the scalability of these machines Bus-based systems therefore have a small number of processors (usually 8), for example, systems with 86 processors, and only more sophisticated interconnection networks allow these systems to scale up to 64 processors For example, in the Sun Enterprise series (van der Steen and Dongarra [193]), systems with low model numbers (eg, 3000) are connected by a bus, whereas the high-end model, the Sun Enterprise 10000, uses a crossbar (see Section 22) for up to 64 processors In contrast, distributed memory architectures with message passing allow a much simpler system design, but their programming becomes more complicated In fact, commodity PCs can be connected via a commodity network (eg, Ethernet) to build a so-called cluster of workstations or PCs (Patterson [147], Sterling et al [181]) The big advantage of distributed memory systems is their much better scalability Hence, it is no surprise that the massively parallel processors (MPPs) are distributed memory systems using message passing with up to hundred thousand processors (eg, Thinking Machines CM-5, Intel Paragon, and IBM Blue Gene/L) Distributed shared-memory architectures try to integrate both approaches They provide the ease of the shared-memory programming paradigm and bene t from the scalability of distributed memory systems, for instance, Cray T3D/T3E, the SGI Origin 2000/3000 series, or the HP SuperDome series (van der Steen and Dongarra [193]) Yet, shared-memory programming of these architectures can have limited ef ciency in as much as the heterogeneous access times to memory are often hidden from the programmer 213 Programming Paradigms and Models Shared-Memory Versus Message Passing Programming The programming paradigms for parallel systems have a strong correspondence to the memory access policies of multiprocessors Fundamentally, one can distinguish between shared-memory and message passing programming In the former paradigm, every processor has full access to the shared memory, and communication between the parallel processors is done implicitly via the memory Only concurrent access to the same memory location needs explicit synchronization of the processors In message passing programming, every exchange of data among processors must be explicitly expressed with send and receive commands It must be noted that the employed programming paradigm does not always correspond to the underlying memory organization of the target system Message passing
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can be utilized on both shared-memory and message passing architectures In a sharedmemory system, the passing of a message is often implemented as a simple memory copy Even distributed shared memory can be emulated on message passing machines with an additional software layer (eg, survey by Proti et al [154]) c Parallel Random Access Machine (PRAM) PRAM (Fortune and Wyllie [68]) is a popular machine model for algorithm design and complexity analysis Essentially, the simple model assumes an ideal centralized shared-memory machine with synchronously working processors PRAMs can be further classi ed according to how one memory cell can be accessed: only exclusively by one processor or concurrently by various processors Memory access to different cells by different processors can always be performed concurrently The advantage of PRAM is its simplicity and its similarity to the sequential von Neumann model Yet, owing to the increasing gap between processing and communication speed, it has become more and more unrealistic LogP With the proposal of the LogP model, Culler et al [46, 47] recognized the fact that the widely used PRAM model is unrealistic due to its assumption of cost-free interprocessor communication, especially for distributed systems The LogP model gained its name from the parameters that are used to describe a parallel system:
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L: Upper bound on the latency, or delay, incurred in communicating a message from a source to a destination processor o: Overhead time during which a processor is engaged in sending or receiving a message; during this time the processor cannot perform other operations g: Gap minimal time between consecutive message transmissions or between consecutive message receptions; the reciprocal of g corresponds to the perprocessor bandwidth P: Number of processors
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