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INTRODUCTION
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The last aspects to be considered in this chapter are genetic algorithms and how they can be applied to the scheduling problem 7 investigates how to handle contention for communication resources in task scheduling The chapter begins with an overview of existing contention aware scheduling algorithms, followed by an outline of the approach taken in this book Next, an enhanced topology graph is introduced, based on a thorough analysis of communication networks and routing Contention awareness is achieved with edge scheduling, which is investigated in the third section The next section shows how task scheduling is made contention aware by integrating edge scheduling and the topology graph into the scheduling process Adapting algorithms for scheduling under the contention model is analyzed in the last section, with the focus on list scheduling 8 investigates processor involvement in communication and its integration into task scheduling It begins by classifying interprocessor communication into three types and by analyzing their main characteristics To integrate processor involvement into contention scheduling, the scheduling model is adapted The new model implies changes to the existing scheduling techniques General approaches to scheduling under the new model are investigated Using these approaches, two scheduling heuristics are discussed for scheduling under the new model, namely, list scheduling and two-phase heuristics
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Parallel Systems and Programming
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This chapter reviews parallel systems and their programming The intention is to establish the necessary background and terminology for the following chapters It begins with the basis of parallel computing parallel systems and discusses their architectures and communication networks In this context, it also addresses programming models for parallel systems The second part of the chapter is devoted to the parallelization process of parallel programming A general overview presents the three components of the parallelization process: subtask decomposition, dependence analysis, and scheduling The subsequent sections discuss subtask decomposition and dependence analysis, which build the foundation for task scheduling
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21 PARALLEL ARCHITECTURES Informally, a parallel computer can be characterized as a system where multiple processing elements cooperate in executing one or more tasks This is in contrast to the von Neumann model of a sequential computer, where only one processor executes the task The numerous existing parallel architectures and their different approaches require some kind of classi cation
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211 Flynn s Taxonomy In a frequently referenced article by Flynn [67], the design of a computer is characterized by the ow (or stream) of instructions and the ow (or stream) of data The taxonomy classi es according to the multiplicity of the instruction and the data ows The resulting four possible combinations are shown in Table 21 The SISD (single instruction single data) architecture corresponds to the conventional sequential computer One instruction is executed at a time on one data item Although the combination MISD (multiple instruction single data) does not seem to be meaningful, pipeline architectures, as found in all modern processors, can be considered MISD (Cosnard and Trystram [45])
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Task Scheduling for Parallel Systems, by Oliver Sinnen Copyright 2007 John Wiley & Sons, Inc
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PARALLEL SYSTEMS AND PROGRAMMING
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Table 21 Flynn s Taxonomy Single Data Single Instruction Multiple Instruction SISD MISD Multiple Data SIMD MIMD
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In SIMD (single instruction multiple data) architectures, which are also called data parallel or vector architectures, multiple processing elements (PEs) execute the same instruction on different data items Figure 21(a) shows the SIMD structure with one central control unit and multiple processing elements The central control unit issues the same instruction stream to each PE, which works on its own data set Especially for regular computations from the area of science and engineering (eg, signal processing), where computations can be expressed as vector and matrix operations, the SIMD architecture is well adapted There are only a few examples of systems that have a pure SIMD architecture, for instance, the early vector machines (eg, the Cray-1 or the Hitachi S-3600) (van der Steen and Dongarra [193]) Today, the SIMD architecture is often encountered within a vector processor, that is, one chip consisting of the central control unit together with multiple processing elements A parallel system can be built from multiple vector processors and examples for such systems are given later Also, most of today s mainstream processor architectures feature an SIMD processing unit, for example, the MMX/SSE unit in the Intel Pentium processor line or the AltiVec unit in the PowerPC processor architecture The second parallel architecture in the taxonomy has MIMD (multiple instruction multiple data) streams, depicted in Figure 21(b) In contrast to the SIMD structure, every PE has its own control unit (CU) Therefore, the processor elements operate
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