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So the primary differences between different levels of caches are their size and access times Figure 1 42 contains a chart that illustrates some rule of thumb measurements of memory access times, in terms of clock cycle time An interesting measure of performance is cycles per instruction (CPl) This is a measure of the average number of cycles each instruction executed by a program (or some subset of the program) consumed This can be used to explain the cache behavior and its impact to performance, specifically whether trips to main memory were frequent A higher CPI means that more time was wasted waiting for memory operations to complete Cache coherence is the act of keeping caches synchronized with what is in main memory We already saw in 1 0, Memory Models and Lock Freedom, that caches, ILP, and write buffering-techniques all used to hide memory access latencies-can cause some real headaches But you have to appreciate the amount of complexity that goes into making it all work Most modern AMD and Intel processors use a directory based snooping structure, which is a fancy way to say that each processor is responsible for watching cache transactions that are going to main memory As cache transactions are witnessed, the processor must update any of its own cache lines, tracking their status, and possibly invalidating local copies so that they are subse quently refetched from main memory when needed
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E is for Exclusive The local processor has exclusive access to the line This is used for interlocked operations such as XCHG Only one processor may have a given line marked as E in its local cache S is for Shared The cache line is valid and may be shared for read access by multiple processors at a given time I is for Invalid Due to snooping a write back to main memory per formed by a separate processor, this line is no longer valid It must be refetched
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Contention arises for all modes but S When processors write to the same cache line a large amount of cache maintenance and memory traffic is gen erated This is expensive, so it is ideal to try and avoid concurrent access by multiple processors to the same memory locations That is particularly true of E mode This is a topic we'll explore in depth momentarily Caches are fixed in size, so another event that would cause lines to be evicted is a cache becoming full Most caches use a least recently used (LRU) policy to determine which lines to evict first in such cases Subse quent access of evicted lines will be satisfied elsewhere in the hierarchy You can query about the layout of the memory hierarchy-to obtain information such as what processors share what levels of cache, whether hyperthreading is enabled, NUMA node layout, and so forth-using the Get Logi c a l P ro c e s so r l nformat i o n function This API was added to Win dows Server 2003 and beats out GetSy ste m l n fo and querying the C P U I D to determine similar information
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The function stores a bunch of interesting data in the array of SYSTEM_LOG ICAL_PROC E S SOR_I N F ORMATION records supplied The number of records is system dependant, so calling the API with a NU L L B uffe r, and Ret u r n L e n gt h of e allows you to determine what the correct buffer size is beforehand The API will return FALS E and Get L a s t E r r o r will be E R ROR_I NSU F F I C I ENT_BU F F E R, but the Ret u r n Length parameter will have received the correct size in bytes You must then allocate a buffer of at least Ret u r n Le n gt h / s i z eof ( SYSTEM_LOG ICAL_P ROC ESSOR_I N F O RMATION ) ele ments After calling the method again with the correct arguments, the array will be populated Each record contains a lot of useful information
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