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Some 64-bit architectures support 1 28-bit 0 6-byte) interlocked operations X86 does not support them at all, most X64 processors do, and IA64 does, but in a different way than X64 Let's first look at what X64 supports Much like the CMPXCHG8B instruction, nearly all X64 processors offer a CMPXCHG 16B that is atomic in the same way that LOCK CMPXCHG is Some early 64-bit AMD chips didn't offer the same level of support as modern X64 chips do, meaning you technically need to use a CPUID to test whether support is present This makes it harder to write
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portable 64-bit code and is the reason why 1 28-bit interlocked operations are hard to find in the Win32 APls and are entirely unsupported in NET Aside from writing assembly, the only current way to access CMPXCHG 168 is to use the _I n t e r l o c kedCompa re E x c h a n g e 1 2 8 c++ intrinsic
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The De s t i n a t ion pointer refers to a 1 28-bit location: that is, two adjacent 64-bit values The E x c h a ngeHigh and E x c h a nge Low values are 64-bit values representing the values to place into the destination And the Compa r a n d
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Re s u lt pointer refers to a 1 28-bit location, such as De s t i n at i o n , that
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contains the 1 28-bit value to use as a comparison: that is, if the current value doesn't equal that stored in Compa r a n d R e s u lt, the CAS will fail It returns 1 to indicate the swap succeeded and 0 to indicate that it failed In either case, after the call Compa r a n d Re s u lt will contain the value seen in D e st i n a t i o n during the attempt As with 64-bit interlocked operations above, this capability can be used to simulate atomic loads and stores of 1 28-bit values The support for 1 28-bit interlocked operations is slightly different on IA64 processors For this architecture, there is an I n t e r l o c k e d
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This operation can be used for situations where the least significant bits contain data to be validated, but the most significant bits are used as a value to be replaced While certainly much less useful in general than a full CMPXCHG168 instruction, this capability can still be used in limited cases, such as to avoid ABA problems with lock free stacks (as we examine later)
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There are also related intrinsics that are preceded with underscores and also acquire and release variants to control the kind of barrier implied by its use These intrinsics also emulate this operation on X64 processors that don' t offer native instructions, although it does so using the aforemen tioned CMPXCHG16B instruction The IA64 processor also supports _loa d 1 2 8 , _sto r e 1 28, and _store1 28J e l intrinsics that enable atomic loads and stores of 1 28-bit data types There is a little-known secret that certain SSE instructions such as MOVDQU provide atomic 1 28-bit operations on some architectures Processors do not guarantee this atomicity, so any implemen tations that happen to provide it are subject to change in the future
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